The present invention relates to a booster circuit for a nonvolatile semiconductor memory device, in particular, a booster circuit having a capacitor made of a dielectric film.
Conventionally, the most widely used flash memories (batch erase type memory) include ETOX (EPROM Thin Oxide: a registered trademark of Intel). FIG. 11 shows a schematic cross sectional view of this ETOX-type flash memory cell. As shown in FIG. 11, a floating gate 5 is formed on a source 1, a drain 2 and a substrate (well) 3 between the source and the drain via a tunnel oxide film 4. Furthermore, a control gate 7 is formed on the floating gate 5 via an interlayer insulating film 6.
The operation principles of the ETOX-type flash memory are explained below. As shown in Table 1, a voltage Vpp (for example, 9 V) is applied to the control gate 7, a standard voltage Vss (for example, 0 V) is applied to the source 1 and a voltage of 6 V is applied to the drain 2 during a write operation. Consequently, a large amount of currents flow into a channel layer, channel hot electrons are generated in a portion on the drain 2 side having a high electric field and electrons are injected into the floating gate 5. As a result, the threshold voltage of a memory cell 8 is increased and data is written to the memory cell 8. FIG. 12 shows a threshold voltage distribution in a written state and an erased state. As shown in FIG. 12, the threshold voltage of the written memory cell is 5 V or higher.
Furthermore, during an erase operation, a voltage Vnn (for example, xe2x88x927.5 V) is applied to the control gate 7 and a voltage Vpe (for example, 4 V) is applied to the source 1. Consequently, the drain 2 is opened, and a strong electric field is generated in the tunnel oxide film 4 between the source 1 and the floating gate 5. Then, electrons are pulled from the floating gate 5 to the source 1 side by Fowler-Nordheim (FN) tunneling to decrease the threshold voltage of the memory cell 8. As a result, the threshold voltage of the erased memory cell 8 becomes 1.5 to 3 V as shown in FIG. 12.
Furthermore, during a read operation, a voltage of 1 V is applied to the drain 2 and a voltage of 5 V is applied to the control gate 7. Here, when the memory cell 8 is in an erased state and has a low threshold voltage, currents flow into the memory cell 8 and a state xe2x80x9c1xe2x80x9d is determined. On the other hand, when the memory cell 8 is in a written state and has a high threshold voltage, currents do not flow into the memory cell and a state xe2x80x9c0xe2x80x9d is determined.
Meanwhile, when a nonvolatile semiconductor memory device using the ETOX-type flash memory cell or the like is driven, for example, in a case where an external power source voltage Vcc is 5 V, voltages other than the externally supplied power source voltage Vcc (5 V) (in the above example, voltages Vpp, Vnn and the like) are required in a drive system of the nonvolatile semiconductor memory device. FIG. 13 shows a block diagram of a voltage generation system in this case.
As shown in FIG. 13, three booster circuits (voltage pumps) are provided in the voltage generation system of the nonvolatile semiconductor memory device. One is a first high voltage pump 14. This first high voltage pump 14 generates a bit line voltage and transmits it to a Y decoder 12 during a write operation to respective memory cells 8 constituting a memory cell array 11. Meanwhile, during an erase operation, the pump generates a source voltage and transmits it to a source switch circuit 13 to apply the voltage to the source 1 of the memory cell 8. It is noted that an output voltage of the first high voltage pump 14 is lowered to 4 V during the erase operation. Another pump is a second high voltage pump 16, which generates a word line voltage during a write operation and transmits it to an X decoder 15. The other pump is a negative voltage pump 17, which generates a negative voltage for a word line (control gate 7) during an erase operation and transmits it to the X decoder 15.
The outputs of the first high voltage pump 14 and the second high voltage pump 16 are used as power sources for a level shifter circuit or the like in the Y decoder 12 and the source switch circuit 13. Table 2 shows values of maximum voltages outputted from the voltage pumps 14, 16, 17.
FIG. 14 shows an example of these voltage pumps generating voltages. FIG. 14 is a circuit diagram of the second high voltage pump 16, which is constituted by a plurality of n-MOS (metal oxide film semiconductor) transistors and a plurality of capacitors. An external power source voltage Vcc is boosted by inputting a clock CLK to output a higher voltage. FIG. 15 shows changes in the voltage of each node with time in this case (for example, in the case of Vcc=5 V). The voltage of each node in FIG. 15 is an average voltage value. Although it is not shown, the voltage is actually amplified in synchronization with the clock CLK. As shown in FIG. 15, the voltage of each node is gradually increased with time and reaches a prescribed voltage for each node. It is noted that the output voltage of the second high voltage pump 16 in this case is 9 V (not shown).
FIG. 16 shows details of a voltage waveform immediately after the voltage of node 4 is increased and reaches the prescribed voltage 11.2 V, that is, a voltage waveform at the encircled point in FIG. 15. As shown in FIG. 16, when the clock CLK2 of Vss is inputted into the capacitor C4 ((0 V)xe2x86x92Vcc (5 V)), the voltage of the node 4 is increased from 7 V to 11.2 V. As a result, a voltage of 9 V on average can be obtained at the output stage. This output voltage of 9 V finally becomes a word line voltage during a write operation.
FIG. 17 shows a circuit of the negative voltage pump 17. It has a basic constitution that is similar to that of the second high voltage pump 16 and is constituted by a plurality of p-MOS transistors and a plurality of capacitors. Furthermore, an external voltage Vss is lowered by inputting a clock CLK to output a negative voltage. FIG. 18 shows changes of the voltage of each node with time in this case. The voltage of each node changes with time and reaches a prescribed voltage for each node. FIG. 19 shows details of a voltage waveform at the encircled point in FIG. 18. As shown in FIG. 19, when the clock CLK2 (Vcc (5 V)xe2x86x92Vss (0 V)) is inputted into the capacitor C4, the voltage of the node 4 is lowered from xe2x88x925.8 V to xe2x88x929.8 V. As a result, a voltage of about xe2x88x927.5 V on average can be obtained at the output stage. This output voltage of xe2x88x927.5 V finally becomes a gate line voltage during an erase operation.
However, the above conventional booster circuit of a nonvolatile semiconductor memory device has the following problems. That is, in the case of the second high voltage pump 16 having a configuration shown in FIG. 14, the voltage of the node 4 is 7 V when the clock CLK2 is 0 V, while it is 11.2 V when the clock CLK2 is 5 V. Therefore, the voltage applied to the capacitor C4 becomes 7 V when the clock CLK2 is 0 V, while it is 6.2 V when the clock CLK2 is 5 V. Here, when the withstand voltage of an insulating film constituting a dielectric film of the capacitor C4 is 6.5 V, a voltage applied when the clock CLK2 is 0 V, which is 7 V, exceeds the withstand voltage. Therefore, the insulating film may be damaged in the worst case.
As one of methods for solving this problem, in a semiconductor integrated circuit disclosed in Japanese Patent Laid-Open Publication No. 5-28786, a thick oxide film is used as a dielectric film for a capacitor that is disposed in the vicinity of the output stage and subjected to a large potential difference between its ends to avoid the above problem of the withstand voltage.
Furthermore, as one of other methods, as shown in FIG. 20A, there is a method wherein a capacitor C is constituted by a two-stage capacitor composed of two capacitors C1, C2 connected in series and a voltage applied to each capacitor C1, C2 is decreased. Here, when a capacity of each of the two-staged capacitors C1, C2 is xe2x80x9c2xc3x97Cxe2x80x9d, the capacity of the capacitors C1, C2 becomes xe2x80x9cCxe2x80x9d when they are two-staged in series.
When this method is applied to the capacitor C4 in FIG. 14 and the node 5 between the two-stage capacitors C1, C2 is an intermediate node, voltage waveforms of the clock CLK2, the node 4 and the intermediate node 5 are ideally as shown in FIG. 21. That is, in FIG. 21, when the voltage of the clock CLK2 is 0 V, the voltage of the intermediate node 5 is 2.3 V, the voltage of the node 4 is 7 V and the maximum applied voltage is 4.7 V. On the other hand, the voltage of the clock CLK2 is 5 V, the voltage of the intermediate node 5 is 7 V, the voltage of the node 4 is 11.2 V and the maximum applied voltage is 4.2 V. Therefore, the maximum voltage applied to each capacitor C1, C2 is 4.7 V and can be suppressed to the aforementioned withstand voltage 6.5 V of the capacitor or lower.
Meanwhile, as shown in FIG. 20B, when one capacitor is achieved by a laminated structure wherein an interlayer insulating film 20 is sandwiched between a first polysilicon film 18 and a second polysilicon film 19 (in practice, when an interlayer insulating film of the memory cell array 11 (see FIG. 11) is formed, a capacitor of a booster circuit is often formed by the same polysilicon film/insulating film/polysilicon film), the intermediate node 5 is in a floating state, thereby receiving no direct potential from other nodes. As a result, the intermediate node 5 is charged up in the initial state, the positive charge can be charged up to, for example, 5 V. The relationship between the voltage transition of the clock CLK2 and the voltage transitions of the node 4 and the intermediate node 5 in this case is shown in FIG. 22. As shown in FIG. 22, the maximum voltage applied to the capacitor C2 becomes 7.3 V and exceeds the withstand voltage of the capacitor insulating film composed of an interlayer insulating film 20. Therefore, the capacitor is damaged in the worst case.
On the other hand, when the negative charge can be charged up to, for example, xe2x88x925 V in the initial state, the relationship of the voltage transition of the clock CLK2 and the voltage transitions of the node 4 and the intermediate node 5 in this case is as shown in FIG. 23. As shown in FIG. 23, the maximum voltage applied to the capacitor C1 becomes 9.7 V and exceeds the withstand voltage of the capacitor insulating film composed of the interlayer insulating film 20. Therefore, the capacitor is damaged in the worst case.
Thus, in the above two-stage capacitor, when the intermediate node is in a floating state, the intermediate node is charged up and either one of the voltages of the both ends of the capacitor may exceed the withstand voltage of the capacitor insulating film. Thus, a problem arises that the insulating film constituting the capacitor may be damaged.
Therefore, as a method for solving this problem in the two-stage capacitor, there is a method wherein a diode is connected to the intermediate node of the two-stage capacitor (in practice, a transistor connected as a diode). For example, as shown in FIG. 24, an n-MOS transistor 21 is connected to an intermediate node 5 between two capacitors C4a, C4b constituting a two-stage capacitor. In this case, when the intermediate node 5 is almost charged to a negative voltage, the charge is discharged into an n-diffusion region or a p-well of the n-MOS transistor, thereby causing no problem. Furthermore, since the intermediate node 5 has a positive potential during an operation, there is no problem. However, when the intermediate node 5 is charged up to a positive charge, there is basically no path to which the charge is discharged and it leads to the situation shown in FIG. 22 in the worst case. Since the voltage applied to the capacitor C4b exceeds the withstand voltage, the capacitor C4b is damaged in the worst case.
Furthermore, as shown in FIG. 25, a p-MOS transistor 22 may be connected to the intermediate node 5 between the two capacitors C4a, C4b constituting a two-stage capacitor. In this case as well, the situation shown in FIG. 22 is basically caused as in the case of FIG. 24, and damage to the capacitor due to a charge-up to a positive charge cannot be avoided.
Furthermore, the negative voltage pump 17 having a configuration shown in FIG. 17 also has the same problem as that of the second high voltage pump 16. That is, a large voltage difference of 10.8 V in maximum is applied to a part of the capacitor C4 in the vicinity of the output stage, wherein the lowest voltage is outputted, as shown in FIG. 19. Here, when the capacitor withstand voltage is 8 V, the capacitor withstand voltage is exceeded and the capacitor C4 is damaged.
Therefore, as in the case of the above high voltage pump, a method wherein the capacitor C4 is two-staged is used to avoid an excess voltage. The circuit configuration is shown in FIG. 26. As shown in FIG. 26, the capacitor connected to the node 4, which has the largest voltage difference, is constituted by two stages. The voltage waveform in this case is ideally as shown in FIG. 27. In this case, the maximum voltage applied to both ends of the capacitor is 6.4 V, which is not higher than the withstand voltage.
However, when a circuit configuration as shown in FIG. 26 is used and the two-stage capacitor C4a, C4b is formed by a xe2x80x9cpolysilicon film/insulating film/polysilicon filmxe2x80x9d, the intermediate node 5 becomes in a floating state and this intermediate node 5 may be charged up. Furthermore, when a negative charge is charged up to this intermediate node 5 in the initial state, voltage waveforms are obtained as shown in FIG. 28. When a positive charge is charged up, voltage waveforms become as shown in FIG. 29. In either case, the withstand voltage of the capacitor, which is 8 V, may be exceeded. Therefore, a problem arises that the capacitor may be damaged.
Accordingly, the object of the present invention is to provide a booster circuit of a nonvolatile semiconductor memory device wherein a stable pump operation can be achieved without charging up an intermediate node between two-stage capacitors.
In order to achieve the above object, there is provided a booster circuit of a nonvolatile semiconductor memory device having a plurality of capacitors, generating a voltage different from a power source voltage during a write operation and an erase operation and supplying the voltage to the nonvolatile semiconductor memory device, wherein
among those capacitors, a capacitor to which a high electric field exceeding a withstand voltage of an insulating film constituting each capacitor is applied is constituted by two or more partial capacitors connected to each other in series; the booster circuit, comprising:
a transistor element connected between the partial capacitors; and
control means, which turns on the transistor element when the nonvolatile semiconductor memory device is in an inoperative state and turns off the transistor element when the device is in an operative state.
According to the above constitution, when the nonvolatile semiconductor memory device is in an inoperative state, a transistor element connected between the partial capacitors constituting a capacitor to which a high electric field is applied is turned on by a control means. Thus, the charge charged to the intermediate node between the partial capacitors is discharged via the transistor element, which is turned on. Therefore, a voltage applied to each capacitor and each partial capacitor during a normal operation does not exceed its withstand voltage and an insulating film constituting the capacitor and the partial capacitors is not damaged.
Furthermore, when an operation of the nonvolatile semiconductor memory device is started, the transistor element is turned off by the control means. Therefore, a stable operation can be performed when the operation of the nonvolatile semiconductor memory device is started.
In one embodiment of the present invention, the transistor element is a p-type metal oxide film semiconductor transistor whose source is connected to a standard voltage; and
the control means is constituted such that the standard voltage is applied to a gate of the p-type metal oxide film semiconductor transistor when the nonvolatile semiconductor memory device is in an inoperative state.
According to this embodiment, when a positive charge is charged to the intermediate node between the partial capacitors, the charge is discharged via a turned-on p-type MOS transistor. On the other hand, a negative charge is charged, the charge is discharged via an N-well of the p-type MOS transistor. Thus, the potential of the intermediate node becomes about 0.7 V. Therefore, the voltage applied to each partial capacitor does not exceed the withstand voltage during a normal operation.
In one embodiment of the present invention, the transistor element is an n-type metal oxide film semiconductor transistor whose source is connected to the standard voltage; and
the control means is constituted such that the power source voltage is applied to a gate of the n-type metal oxide film semiconductor transistor when the nonvolatile semiconductor memory device is in an inoperative state.
According to this embodiment, a positive or negative charge charged to the intermediate node between the partial capacitors is discharged via the turned-on p-type MOS transistor. Thus, the potential of the intermediate node is maintained at the standard voltage and not charged up. Therefore, the voltage applied to each partial capacitor during a normal operation does not exceed the withstand voltage and the capacitor cannot be charged up.
In one embodiment of the present invention, at least the partial capacitor has a structure including polysilicon, an insulating film and polysilicon laminated in this order.
According to this embodiment, since each of the partial capacitors constituting a multiple-stage capacitor has a stacked structure of polysilicon/insulating film/polysilicon, the intermediate node becomes in a floating state and is easily charged up. However, since the charge of the intermediate node is discharged via the turned-on transistor element, the voltage applied to each partial capacitor during a normal operation does not exceed the withstand voltage.
In one embodiment of the present invention, the voltage different from the power source voltage is a high voltage higher than the power source voltage.
According to this embodiment, the intermediate node between the multiple-stage capacitors is not charged up and a stably operatable booster circuit for a high voltage can be obtained.
In one embodiment of the present invention, the voltage different from the power source voltage is a negative voltage.
According to this embodiment, the intermediate node between the multiple-stage capacitors is not charged up and a stably operatable booster circuit for a negative voltage can be obtained.